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Beyond Moore, Samsung's road to heterogeneous integration

Release on : Oct 11, 2021

Beyond Moore, Samsung's road to heterogeneous integration
Samsung Moore Heterogeneous Integration
At the recently held SamsungFoundry Forum in 2021, Samsung revealed the new progress of the 2/3nm process technology, and publicly released a new 17nm process. MoonSoo Kang, Samsung’s vice president of marketing strategy, also announced Samsung’s plan for heterogeneous integration and how to add another “dimension” to Moore’s Law for industry partners.

Comparison of area changes between flagship GPUs and mobile chips / Samsung

For decades, the semiconductor industry has been unremittingly promoting Moore's Law, using more advanced processes to achieve more transistors. This is what we often call the "continuation of Moore" solution, and it is also the biggest driving force for continuous innovation in the current computing and circuit fields. force.
Despite the continuation of Moore's Law, the chip area is still expanding. For example, the GPU, which has been pursuing computing power, is approaching the limit of the mask size. Coupled with the increase in the number of transistors, the cost of chip design and production has increased endlessly. In the eyes of many people, relying solely on "Continuing Moore" is no longer a technically and cost-sustainable solution.

At the same time, more functions and features are integrated on a single chip, but there is no single process that can meet the needs of all different functions, such as analog, radio frequency, high voltage, etc., even if it can be met, it cannot achieve excellent performance and cost balance. The "Continuation of Moore" program is helpless in the face of such challenges, so the "extended Moore" program of heterogeneous integration has emerged. Through the complementation of the two programs, we will jointly achieve "Beyond Moore".

Chiplet: a savior to reduce costs and increase yield

With the addition of more features to a single chip, even if Moore's Law continues, its chip area is still increasing. Using the same process node for all design blocks with different functions has become an offset choice. Fortunately, Chiplet is now a savior. Appear. Dividing a large piece of die into smaller chiplets and using the optimal manufacturing process for each chiplet can significantly increase the yield of the entire chip while reducing production costs. For example, some specific interface IPs will not be optimized in area or performance due to the use of advanced manufacturing processes. Using mature manufacturing processes and dedicated custom manufacturing processes for these IPs can achieve lower costs and better performance.

Chiplet Solution / Samsung

Another feasible solution is modular design and manufacturing, which is to reuse the same component chiplet. Many IP modules can be reused as chiplets. Only the other parts of the chip need to be redesigned and produced. This significantly reduces the cost of design, development and production, and chip manufacturers can use this to achieve product iterations faster.

X-Cube: Vertical 3D integration

Heterogeneous integration is not only for cost and yield considerations, but can also further improve chip performance. In traditional 2D designs, the signal path is several millimeters long. Under 3D integration, the stacking of chips can reduce the signal path to a few microns, greatly improving chip delay. In addition, the better inline spacing in 3D integration can achieve higher bandwidth and further improve chip performance.

As early as 2014, Samsung realized the 3D stacking of wide IO memory and mobile application processor for the first time, which is Samsung's Widcon technology. Subsequently, 3D chip stacking technology continued to develop, and a series of HBM memory products were born. HBM is formed by stacking DRAM and logic, and connecting micro bumps and TSVs. It is precisely because of the 3D stacking technology that Samsung was able to develop a three-layer CMOS image sensor, which is made up of image sensors, logic and DRAM three different die stacked together.

In 2020, Samsung introduced the X-Cube technology, which allows two logic unit die to be stacked vertically to form a single 3D chip, which is connected to TSV by micro bumps. X-Cube is divided into two forms, the two dies are connected by micro bumps or direct copper bonding.

X-Cube roadmap / Samsung

The first generation of X-Cube technology (u-Bump) mainly relies on micro bump connection. Samsung has released TSV PDK for 7nm logic process, using F2B structure, bump pitch is 40um. The TSV PDK for 4/5nm has also been released, using the F2F structure, and the bump pitch is reduced to 25um. The second-generation X-Cube technology (Bump-less), which is still under development, uses direct copper bonding technology, and the pitch is reduced to 4um.

It is worth mentioning that Intel's Foveros3D stacking technology route is roughly the same as that of Samsung X-Cube. The bump pitch of the first generation Foveros is between 36um and 50um, and the next generation FoverosOmni technology can also achieve a bump pitch of 25um. Foveros Direct, which is still under development, also uses direct copper bonding, claiming that the bump pitch is reduced to less than 10um.

In the past X-Cube architecture, the area of ​​the bottom die was larger than that of the top die. However, in order to better meet customers' different requirements for chip partitioning and heat dissipation, Samsung will also provide a structure where the top die is larger than the bottom die in the future. . At present, Samsung has completed the verification of 3D stacked SRAM. Under the 7nm process, it can achieve a bandwidth of 48.6GB/s, as well as a read delay of 7.2ns and a write delay of 2.6ns.

In addition, Samsung also provides a differentiated technology, ISC (Integrated Stacked Capacitor). This capacitor applies the silicon capacitor structure, material and process that have been verified in Samsung DRAM products, and has a capacitance density of 1100nF/mm2, which can effectively improve power integrity. Samsung's ISC also provides a variety of different configurations, such as discrete type, silicon interposer type and multi-wafer stack type to meet the different structural needs of customers. ISC is expected to enter the mass production stage in 2022.

I-Cube: Horizontal 2.5D combination

On the other hand, in order to combine chips horizontally, Samsung has developed the so-called 2.5D technology I-Cube, which integrates logic cells and multiple HBMs on the same silicon interposer. At present, Samsung has successfully achieved mass production of one logic die + two HBM I-Cube2, and one of the finished products is Baidu's Kunlun AI chip. Baidu's Kunlun AI chip not only uses Samsung's 14nm process, but also Samsung's I-CUBE 2 technology.

I-Cube uses pre-screening technology to perform operational testing in the intermediate stage of packaging to improve yield. The technology also uses an unencapsulated structure to achieve better heat dissipation performance. According to Samsung, the heat dissipation efficiency of I-Cube is 4.5% higher than that of the traditional 2.5D solution. In addition, compared with other foundries, Samsung’s I-Cube technology has some advantages. For example, it cooperates with Samsung Memory and is the first to use the latest memory solutions.

I-Cube4 schematic / Samsung
Samsung is currently planning mass production of I-Cube4 integrated with 4HBM3 modules, and 6 HBM I-Cube6 is also ready for mass production. The former is expected to enter mass production in 2022. Samsung has even prepared an I-Cube8 solution with two logic dies + 8 HBMs. It is still in the development stage and is expected to be officially launched at the end of 2022.

2D to 3.5D packaging solutions / Samsung

In addition to 2D, 2.5D and 3D IC technology, Samsung is also developing a new 3.5D packaging technology. This system-in-package will also add stacked custom DRAM or SRAM die to achieve higher performance and density.


When developing 2.5D/3D integrated multi-chip or multi-Chiplet system-on-chip, designers often encounter technical obstacles that are rare in traditional single-chip design, such as additional interface IP or potential power consumption increase. At this time, Samsung, TSMC, and Intel, which has just entered IDM 2.0, will also provide heterogeneous design methods and tools to help designers overcome these challenges. Under the general trend of heterogeneous integration, foundries will also provide more service models, adding packaging, testing and one-stop design services.