CY2291 is the third generation of clock generator series. The CY2291 is upward compatible with industry standard ICD2023 and ICD2028 by providing its traditional high level of customizable features to meet different clock synchronization systems. All components provide a highly configurable shutdown feature board application for the PC. Each of the four configurable clocks (CLKA-CLKD) can be assigned any combination of one of 30 frequencies. Multiple outputs are configured with the same or associated frequency with low (<500 ps) skew, which actually provides on-chip buffering for heavy load signals.
The CY2291 can be configured for 5 V or 3.3 V operation. The internal ROM table uses EPROM technology, allowing full custom output frequency. The reference oscillator is designed for 10 MHz to 25 MHz crystals with additional flexibility without the need for external components for this crystal. Alternatively, the external reference clock can use frequencies between 1 MHz and 30 MHz. Customers using a 32 kHz oscillator must be connected to a 10 M resistor in parallel with the 32 kHz crystal.
Three integrated phase-locked loops
Factory Programmable (CY2291) or Field Programmable (CY2291F) Device Options
Low offset, low jitter, high precision output
Power Management Options (Shutdown, OE, Suspended)
Frequency selection option
CPUCLK smooth rotation
Configurable 3.3 V or 5 V operation
20-lead SOIC package
Logical block diagram:
Pin lead diagram:
20-pin SOIC pinout
Function overview, output configuration:
The CY2291 has five independent frequency sources on the chip. These are the 32kHz oscillator, the reference oscillator and three phase-locked loops (PLLs). Each PLL has a specific function. The system PLL (SPLL) drives the CLKF output and provides a fixed output frequency on the configurable output. The SPLL provides the most output divider options. The CPU PLL (CPLL) is controlled by a select input (S0-S2) to provide between eight user selectable frequencies and a smooth swing frequency. The Utility PLL (UPLL) provides the most accurate clock. It is typically used for miscellaneous frequencies provided by other frequency sources. All configurations are EPROM programmable, providing short-circuit samples and production lead times.
Power saving function:
When pulled out, the SHUTDOWN / OE input tristate output LOW (32 kHz clock output is unaffected). If the system is disabled, a low on this pin also turns off the PLL, counter, reference oscillator, and all other valid components. The current generated on the VDD pin is less than 50A plus 15 15A maximum is typically 10A for a 32-kHz subsystem. After leaving the shutdown mode, the PLL must be relocked. All outputs except 32K have a weak pull-down output and do not float when they say three. The S2 / SUSPEND input can be configured to turn off a customizable output and/or PLL bank when a low level. All PLLs except the 32K output can be turned off almost any combination. The only restriction is that if the PLL is turned off, all outputs derived from it must also be turned off. Pause the PLL to turn off all relevant logic while simply suspending the output forced tristate condition. The CPUCLK can smoothly convert (convert) the maximum output frequency between 8 MHz and 8 MHz (100 MHz at 5 V / 80 MHz for 3.3 V for commercial temperature). This feature is very useful for "green" PC and laptop applications, which can save considerable power by reducing the operating frequency. This feature meets the swing requirements of all 486 and Pentium processors.
CyClocks is an easy to use application that allows you to configure any EPROM programmable clock provided by Cypress. You can specify the input frequency, PLL and output frequency and different function options. Please note that the output frequency range in this datasheet ensures that you remain within limits when specified. CyClocks also has a power calculation feature that lets you see the power consumption of a particular configuration.
All outputs, duty cycle and rise/fall time
Output tristate timing